1. Field of the Invention
The present invention generally relates to a semiconductor device and a manufacturing method thereof, and particularly relates to the semiconductor device that has multilayer interconnection structure, and the manufacturing method thereof.
2. Description of the Related Art
Miniaturization of wiring design rule of semiconductor devices is progressing with rapid development of ULSI (Ultra Large Scale Integration) technology. The number of elements that should be integrated is increasing, and wiring is becoming complicated by the large scale integration. Multilayer interconnection attracts attention in order to cope with this situation.
In the multilayer interconnection, however, delay due to complicated wiring is a concern, and Cu wiring is attracting attention because of a low resistance value, especially in wiring of logic LSIs.
FIG. 1 is a figure explaining wiring structure of a conventional semiconductor device.
With reference to FIG. 1, a silicon dioxide (SiO2) film 11 is formed as an inter-layer film in a device (not shown) formed on a semiconductor substrate 10. On the SiO2 film 11, Cu wiring 15 is formed as lower layer wiring through a barrier metal layer 13 that is made of a material such as tantalum nitride and tantalum.
Further, an SiO2 film 17 is formed on the SiO2 film 11, as an inter-layer film, wrapping the Cu wiring 15. A via plug 21 is formed such that the SiO2 film 17 is penetrated and the Cu wiring 15 is touched through a barrier metal layer 19 that is made of a material such as tantalum nitride and tantalum.
Further, on SiO2 film 17, Cu wiring 23 serving as upper wiring is formed contiguously with the via plug 21 that touches the Cu wiring 15 through the barrier metal layer 19 that is made of a material such as tantalum nitride and tantalum. Further, on the SiO2 film 17, an SiO2 film 25 is formed, contacting with the barrier metal layer 19.
For example, when current flows from the Cu wiring 23 to the Cu wiring 15 through the via plug 21, an electron flows from the Cu wiring 15 to the Cu wiring 23 through the via plug 21.
At this time, the copper atom in the via plug 21 tends to move toward the direction of the Cu wiring 23, like electron flow, according to an electro migration phenomenon. Consequently, a void occurs on the side of the Cu wiring 15 of the via plug 21, due to the copper atom in the via plug 21 moving.
In conventional aluminum (Al) wiring used in logic LSI wiring, tungsten (W) has been used for the via plug. Developments have been made such that the migration of aluminum is suppressed, life distribution of aluminum wiring is suppressed, and high reliability is available.
Recently, in consideration of high-speed processing, practices are shifting to use Cu wiring that has a lower electric resistance than aluminum wiring. As for the Cu wiring, dual damascene processing is being established. All elements of a lamination, wiring—via plug—wiring, are made of Cu. Since the atomic weight of Cu is larger than aluminum, Cu is more resistive against electro migration. However, local current concentration still arises to a via plug in the Cu wiring laminated structure that is miniaturized, causing a poor wiring by a void generated as explained above.
Since the lower resistance of the Cu wiring is a highly desirable matter, wiring structure that can suppress the electro migration of Cu is desired, with attention paid to structure of the via plug.